The present disclosure relates generally to an integrated circuit device and, more particularly, to a native transistor (e.g., nMOSFET) and method of fabrication of a device using a finFET compatible process.
As technology progresses, the desire to create smaller integrated circuit devices increases. For example, the semiconductor industry ardently strives to decrease the size of memory cells. One strategy that has been employed includes the use of multiple gate transistors, otherwise known as FinFETs. A typical finFET device is fabricated using a silicon fin raised from the semiconductor substrate. The channel of the device is formed in the fin, and a gate is provided over (e.g., surrounding) the fin—for example, in contact with the top and the sidewalls of the fin. The gate surrounding the channel (e.g., fin) is beneficial in that allows control of the channel from three sides.
The conventional finFET design may not be feasible to provide a native transistor (e.g., a native finFET NMOSFET) however. The thin channel of a conventional finFET device may be fully depleted. The threshold voltage is controlled by the work function of the gate. Thus, channel doping may be unable to sufficiently modify the threshold voltage of a finFET device. Therefore, there are difficulties in providing a native device (e.g., a device having an approximately zero volt threshold voltage) using a conventional finFET design.
Therefore, what is needed is a transistor structure and method of fabrication compatible with finFET devices and processes.